The present invention relates to a semiconductor memory device, and more particularly to the arrangement of a redundant cell array for a semiconductor memory device.
The higher integration of semiconductor memory devices increases the number of malfunctional memory cells on a chip. Due to this, all semiconductor memory devices now include a redundant cell array besides the normal memory cell array. A poor memory cell of the normal memory cell array is replaced with a memory cell of the redundant cell array. In order to carry out the replacement, in a column redundancy method for instance, a column decoder for the redundant memory cells decodes a column address to select a poor memory cell so as to designate a redundant memory cell's column corresponding to the poor memory cell's column.
FIG. 1 shows a conventional arrangement of a redundant cell array. Referring to FIG. 1, a dotted block N is a normal memory cell array, and a dotted block R is a redundant cell array. Word line WL and bit line BL intersections are shown as either small hollow circles or small filled-in circles. Logic "0" cells are represented by the small filled-in circles, while the small hollow circles are the logic "1" cells. Here, the memory cell of data level "1" may be changed with the memory cell of data level "0". A column select line (CSL) signal CSL0, CSL1, is a signal output from a normal column decoder (not shown), and a redundant column select line (RCSL) signal RCSL0, RSCL1 is a signal output from a redundant column decoder (not shown).
The CSL and RCSL signals are applied as high logic signals when selecting a column and as low logic signals when not selecting a column.
According to the construction of FIG. 1, the bit lines are arranged in order, i.e., 0101, 1010, 0101, etc. If a poor cell exists in a pair of bit lines BL0, for instance, a redundant column select signal is applied to redundant memory cell array R to replace the poor bit lines BL0 with a pair of redundant bit lines RBL0. Further, if poor cells exist in bit line cells BL0 and BL2, for instance, these poor bit line cells BL0 and BL2 are replaced with redundant bit line cells RBL0 and RBL2, respectively, according to the above process and thereby performing a repair operation. However, if poor cells exist in bit line pairs BL0 and BL4 of the normal memory cell array N, the poor cells of bit line pair BL0 are precisely repaired with redundant bit line pair RBL0. However, bit line pair BL4 of the poor bit lines is not repaired with redundant bit line pair RBL2. This is because, according to this memory cell array construction, bit line pairs BL4 and BL5 and redundant bit line pairs RBL2 and RBL3 are conversely connected to input/output lines I/O.sub.0 and I/O.sub.0 and I/O.sub.1 and I/O.sub.1. In other words the arrangement of bit line pairs BL4 and BLB is "0101" but the arrangement of redundant bit line pairs RBL2 and RBL3 is "1010". This does not allow for normal one-for-one replacement. This makes it impossible to precisely analyze a redundant cell during the test of a repaired chip so that it is difficult to detect the presence of a poor transistor or, to test the refresh period.